The invention relates to a semiconductor device and in particular to a pad structure.
Parasitic capacitance typically exists between a pad and substrate of a semiconductor device such as an RF chip, serving as a noise delivery path.
FIG. 1 is a cross-section of a pad structure disclosed in U.S. Pat. No. 5,652,689 by Lee. Electrically isolated N-doped region 31, P wells 33 through 35, and N-doped region 32 are formed on an N-type substrate 32. The P well 33 comprises a P-doped region 33a and an N-doped region 33b, the P well 34 comprises a P-doped region 34a, and the P well region comprises a P-doped region 35a and an N-doped region 35b. A dielectric layer 28 is disposed on the substrate 27, exposing the P-doped region 34a. A pad 26 is disposed on the dielectric layer 28, electrically connecting the P-doped region 34a via a plug 29. As shown, the dielectric layer 28 is between the electrically conductive pad 26 and P wells 33, 35, and thus, parasitic capacitance is, inherently generated between the pad 26, dielectric layer 28, and P well 33, and between the pad 26, dielectric layer 28, and P well 35, serving as noise delivery paths.
FIG. 2 is a cross-section of a pad structure disclosed in TW 429522 by Huang el., wherein a substrate 100 comprises electrically isolated drain region 106 and source region 110. A dielectric layer 116 is disposed on the substrate 100, exposing the drain region 106. A pad 122 is disposed on the dielectric layer 116, electrically connecting the drain region 106 via a plug 120. As shown, the dielectric layer 116 is between the electrically conductive pad 122 and source region 110, and thus, parasitic capacitance is inherently generated between the pad 122, dielectric layer 116, and source region 110, serving as a noise delivery path.